1. Field of the Invention
This invention relates to a semiconductor integrated circuit in which an integrated injection logic device (hereafter referred to as IIL) and other semiconductor devices are integrated on a monolithic semiconductor chip.
2. Description of the Prior Art
Integrated injection logic devices (IIL: H. H. Berger and S. K. Wiedmann: "Merged-Transistor Logic (MTL)--A Low-Cost Bipolar Logic Concept", IEEE J. of SSC, sc-7, 5, p. 340-346 (1972, Oct.); K. Hart & A. Slob: "Integrated Injection Logic--A New Approach to LSI" IEEE J. of SSC, sc-7, 5, p. 346-351 (1972, Oct.)) are now widely used in practice as bipolar logic devices having a high packing density and consuming only small power for operation. The IIL also has a noteworthy advantage that it can be formed on a monolithic semiconductor chip on which a bipolar IC having a conventional constitution is to be formed. On the other hand, the IC having an thin epitaxial-grown semiconductor layer whose small thickness is optimal for the integration of an IIL, has a drawback that the breakdown voltage of the incorporated NPN transistor is usually reduced to less than 10 V. In the case, however, where an IIL and, for example, a linear circuit are integrated on a single semiconductor chip, it is often necessary for the NPN transistors used in the linear section or the driver section to have a breakdown voltage in a range of 15 V-60 V or more. Accordingly, the NPN transistors which are formed along with an IIL on the same chip, must have higher breakdown voltages.
It is also necessary to increase the operational speed of the IIL. The IIL usually has a medium speed in operation and a minimum delay time tpd.sub.min per gate of 20-30 ns. Naturally, this numerical value will change depending on the structure of the IIL in question. It has been reported that in an IIL wherein only the operational speed is taken into consideration a tpd.sub.min of several ns can be attained at the sacrifice of the breakdown voltage (in this case, the breakdown voltage is several volts). If the thickness of the epitaxial layer is increased to obtain a breakdown voltage of several tens of volts and if according to the conventional concept the IIL gate is surrounded by the deep collar region of N.sup.+ -type conductivity, then the resultant tpd.sub.min is longer than 50 ns, which falls under the low speed operation.
It is moreover necessary in the large-scale manufacture of such LSI circuits as described above that large manufacturing tolerances can be allowed. In general, an IIL device is constituted mainly of inverse NPN transistors in which the most deeply formed N-type layers are used as emitters, and therefore essentially has a small current gain .beta.i. Accordingly, if, for example, the base widths of the formed NPN transistors are not uniform, the values of the hFE's of the NPN transistors also become uneven. Therefore, the unevenness of the dimensions of the corresponding constituent regions of the NPN transistors greatly affects parameters such as hFE etc. so that large manufacturing tolerances cannot be obtained for those parameters. In the case of high-breakdown-voltage structures heretofore reported, the manufacturing tolerances are often reduced further than in an ordinary structure. In most of such cases, the large-scale manufacture becomes impossible.
Before the explanation of this invention, two examples of the conventional IIL device will be described concerning their features and drawbacks.
FIG. 1 shows the first exemplary structure which has already been proposed as "phosphorus-buried emitter type IIL device" in the Japanese Patent Application Laid-Open No. 51-116687 which has been assigned to the same assignee as the present invention. In this example, the resistivity of the N-type layer 3 is 1-2 .OMEGA.cm and the thickness of the layer 3 is 9-10 .mu.m so that the breakdown voltage of the NPN transistor is as high as 17-25 V. On the other hand, the phosphorus-buried N.sup.+ -type layer 22 is formed around the antimony-buried N.sup.+ -type layer 21 in the IIL section 201 in such a manner that the layer 22 is contiguous with the P-type base region 52. As a result of this arrangement, the thickness of the N-type layer 3 in the IIL section 201 is substantially reduced. In this structure, the N-type layer 3 beneath the base region 52 in the IIL section is replaced by the extended portion of the phosphorus-buried layer 22. Accordingly, the amount of carriers stored beneath the base region 52 is considerably reduced so that the operational speed of the IIL can be improved, the minimum delay time tpd.sub.min reaching as small a value as 10 ns.
On the other hand, this structure has the following drawbacks. First, use is made of the difference between the degrees of the up-diffusions in the different materials, i.e. the phosphorus-buried and the antimony-buried layer so that there is a limit to the thickness of the usable N-type layer 3. Therefore, the breakdown voltage is at best about 25 V. Secondly, the degree of the unevenness of the thickness of the N-type layer 3 is substantially the degree of the unevenness of the contact of the phosphorus-buried layer 22 with the base region 52 of the IIL section. It is therefore necessary to precisely control the unevenness of the thickness of the N-type layer 3 within a range of .+-.5%. This results in the increase in the production cost, though to a small extent.
FIG. 2 shows the second example of the conventional IIL (1977 International Electron Device Meeting (IEDM), Technical Digest pages 175-177, "A High-Voltage Analog-Compatible IIL Process" (K. J. Allstot et al)). In this example, phosphorus ions are implanted into that part of the surface of the semiconductor substrate which forms an IIL section, so that an N-type well region 41 is brought into existence. As a result of this N-type well region 41, the impurity concentration in the N-type layer 3 of the IIL section is increased to obtain a sufficient current gain in the IIL section. According to this structure, an NPN transistor having a breakdown voltage of higher than 30 V and an IIL circuit can coexist in a monolithic chip.
The first drawback of this structure, however, is that its operational speed is very low. For, since the impurity concentration of the N-type well 41 is lower than that of the layer 21 or 22, more carriers are stored in the N-type well 41. The resultant minimum delay time is about 40 ns.
The second drawback of this structure is that the manufacturing tolerances for hFE is very small. The reason for this is as follows. In the case, for example, where an N-type layer 3 having a breakdown voltage of 30 V is employed, the gap between the bottom of the P-type base region 52 and the top of the antimony-buried layer 21 is usually longer than 2 .mu.m. It is therefore necessary to increase the impurity concentration in the gap up to the value for which an injection efficiency necessary for the operation as IIL can be obtained, by the only addition of the impurity concentration of the N-type well thereto. Accordingly, the N-type well 41 here used must have a much higher impurity concentration than these used in MOS IC's. Since this N-type well is formed through the diffusion of impurity from the top surface downward, there naturally exists a gradient of impurity concentration. Therefore, the impurity concentration near the surface of the N-type well becomes higher, that is, as high as nearly 5.times.10.sup.16 -10.sup.17 atoms/cm.sup.3. This causes the upper shift of the position of the PN junction in the base region 52 of the IIL section so that the base width of the inverse NPN transistor is lessened, the collector-emitter short-circuit tending to occur. This is why the manufacturing tolerance for the base width must be small. According to the Inventors' experiments, the value for hFE of the NPN transistor 101 could be allowed to be distributed within a range of 200.+-.50 to obtain a breakdown voltage of higher than 30 V. This is very severe requirement in mass production.